design of sequential logic using always block:

The Sequential circuit which is going to design is shown in following figure.

With Blocking assignments:

Case-1:

always@( posedge clk) begin

    b = a;

    c = b;

    d = c;

end

In above case b,c are treated as temporary signals because after assigning some value to b & c immediately they are assigned to other signals. so there is no need to remember previous values. so b & c are treated as temporary signals.

Simulation results:

Before applying clk 'a' is set to 0 then b = 0, c = 0, d = 0. In this case simulation and synthesis results are mismatched.

Synthesis results:

Case-2:

always@( posedge clk) begin

    d = c;

    c = b;

    b = a;

end

Simulation Results:

In this case b, c are not temporary because before assigning some value to c, c is assigned to d i.e., c need to be retained its previous value only when c is a memory element. similarly b. Simulation results are d = 1, c = 0, b = 0, a = 0. Simulation results and synthesis results are matched.

Note:  while designing seq logic with blocking assignments ordering of statements (i.e., from output to input) is important.

Synthesis Results:

Case-3:

  always@(posedge clk) begin

    b = a;

  end

  always@(posedge clk) begin

    c = b;

  end

  always@(posedge clk) begin

    d = c;

  end

Simulation results:

Simulation results are same as case-2 if they are executed in the same order as they declared. if the order of execution of always blocks changes then output also changes i.e., race condition. Synthesis results are same as case-2. out of case-2 & 3, case-2 is best because of no race condition.

Synthesis results:

With Non-Blocking Assignments:

Case-1:

 always@(posedge clk) begin

    b <= a;

    c <= b;

    d <= c;

  end 

Case-2:

  always@(posedge clk) begin

    d <= c;

    c <= b;

    b <= a;

  end

Case-3:

  always@(posedge clk) begin

    b <= a;

  end

  always@(posedge clk) begin

    c <= b;

  end

  always@(posedge clk) begin

    d <= c;

  end

Simulation results:

Simulation results results for the above all three case are same and their values are a = 0, b = 0, c = 1, d = 0. For evaluation of NBA please refer procedural assignments concept. Synthesis results are also same for the above all three cases as shown below.

Note: NBA gives same simulation and synthesis results for all three combinations of always block. So, it is always preferable that sequential logic is designed NBA only

Synthesis results: