Self-Triggered always block:

Case-1: always with BA

Assume the initial value of clock is 0.

always@(clock) begin

  #5 clock =~ clock;

end

Here the assignment is blocking i.e., active event. so, it is executed in current tick i.e., after 5 time units clock becomes 1 ans simulator comes out of the loop and watching event to be triggered but it will never happens because the change occurred when the simulator is with in the always block. so, always block executed only once. It is non self triggered always block.

Case-2: always with NBA

Assume the initial value of clock is 0.

always@(clock) begin

  #5 clock <=~ clock;

end

Here the assignment is non blocking i.e., NBA event. so, the evaluation of R.H.S happens in current tick and assignment happens at the end of tick i.e., clock value is evaluated as 1 and the simulator comes out of always block and watching sensitivity list. At the end of tick 1 is assigned to clock. Here simulator sees the change of sensitivity list so always block executed continuously till the end of simulation. It is self triggered always block. It can be used for clock generation in verification.

Stratified event queues:

Stratified event queue model will help us how the various statements like blocking, non blocking, $display,...etc inside module gets executed.

According to the Verilog IEEE standard, the Verilog event queue is logically segmented into four different regions as shown below.

1) Active events:

Active events include continuous assignments, blocking assignments, evaluation of R.H.S of non blocking assignments, $display statements, evaluation of inputs and updation of outputs of primitive gates and other module instances. The above events can be executed in current simulation time in any order.

2) In active events:

After completing execution of active events, inactive events are processed. Here #0 (zero delay statements ) are scheduled.

3) NBA:

Assignment of evaluated things of R.H.S in active region to L.H.S happens after processing active and inactive events. After assigning a value to a variable that may or may not triggers the other always block. If it triggers then that always block is executed in current simulation time only that's why simulator will go to active after NBA.

4)Monitoring:

After NBA if no always block triggers then monitoring events are evaluated. $strobe, $monitor are monitoring events. if simulator loops from NBA to active 100 times and each loop contains one monitoring statement then 100 monitoring statements are stored in a queue, when the simulator comes out of the loop then all 100 monitoring statements are evaluated.

Example:

always@(x,y) begin

  z = x | y;

  a <= z;

end

always@(a) begin

  w = a;

end

Here if x or y changes then first blocking assignment i.e., z is updated and that is evaluated value on R.H.S of NBA. At the end of tick z is assigned to a that indirectly triggers the other always block. Blocking assignment executed and then simulator advances the time i.e., next time tick.

 Design of Combinational logic using always block

The Combinational circuit which is going to be designed is shown in below figure:

Case-1:

  always@(a,b,c,d) begin

    x = a & b;

    y = c & d;

    f = x & y;

  end

Simulation results:

After applying input2 values then x = 1, y = 0 and f = 0. Here simulation results are matched.

Case-2:

  always@(a,b,c,d) begin

    x <= a & b;

    y <= c & d;

    f <= x & y;

  end

Simulation results

After applying input2 values then x = 1, y = 0 and f = 1. Here we get 'f' based on past values of x and y. Here simulation results are mismatched.

Case-3:

  always@(a,b,c,d,x,y) begin //or always@(*) begin

    x <= a & b;

    y <= c & d;

    f <= x & y;

  end

Simulation results:

First always block executed then x and y are evaluated as 1 and 0, f as 1 which is past output. Here y value is changed so always block get executed one more time then f become 0. Here always block gets executed twice, so simulation time become double i.e., performance degrades.

Synthesis results:

Synthesis results for the above all three cases are same as shown below.

design of sequential logic using always block:

The Sequential circuit which is going to design is shown in following figure.

With Blocking assignments:

Case-1:

always@( posedge clk) begin

    b = a;

    c = b;

    d = c;

end

In above case b,c are treated as temporary signals because after assigning some value to b & c immediately they are assigned to other signals. so there is no need to remember previous values. so b & c are treated as temporary signals.

Simulation results:

Before applying clk 'a' is set to 0 then b = 0, c = 0, d = 0. In this case simulation and synthesis results are mismatched.

Synthesis results:

Case-2:

always@( posedge clk) begin

    d = c;

    c = b;

    b = a;

end

Simulation Results:

In this case b, c are not temporary because before assigning some value to c, c is assigned to d i.e., c need to be retained its previous value only when c is a memory element. similarly b. Simulation results are d = 1, c = 0, b = 0, a = 0. Simulation results and synthesis results are matched.

Note:  while designing seq logic with blocking assignments ordering of statements (i.e., from output to input) is important.

Synthesis Results:

Case-3:

  always@(posedge clk) begin

    b = a;

  end

  always@(posedge clk) begin

    c = b;

  end

  always@(posedge clk) begin

    d = c;

  end

Simulation results:

Simulation results are same as case-2 if they are executed in the same order as they declared. if the order of execution of always blocks changes then output also changes i.e., race condition. Synthesis results are same as case-2. out of case-2 & 3, case-2 is best because of no race condition.

Synthesis results:

With Non-Blocking Assignments:

Case-1:

 always@(posedge clk) begin

    b <= a;

    c <= b;

    d <= c;

  end 

Case-2:

  always@(posedge clk) begin

    d <= c;

    c <= b;

    b <= a;

  end

Case-3:

  always@(posedge clk) begin

    b <= a;

  end

  always@(posedge clk) begin

    c <= b;

  end

  always@(posedge clk) begin

    d <= c;

  end

Simulation results:

Simulation results results for the above all three case are same and their values are a = 0, b = 0, c = 1, d = 0. For evaluation of NBA please refer procedural assignments concept. Synthesis results are also same for the above all three cases as shown below.

Note: NBA gives same simulation and synthesis results for all three combinations of always block. So, it is always preferable that sequential logic is designed NBA only

Synthesis results: