Design of Combinational logic using always block

The Combinational circuit which is going to be designed is shown in below figure:

Case-1:

  always@(a,b,c,d) begin

    x = a & b;

    y = c & d;

    f = x & y;

  end

Simulation results:

After applying input2 values then x = 1, y = 0 and f = 0. Here simulation results are matched.

Case-2:

  always@(a,b,c,d) begin

    x <= a & b;

    y <= c & d;

    f <= x & y;

  end

Simulation results

After applying input2 values then x = 1, y = 0 and f = 1. Here we get 'f' based on past values of x and y. Here simulation results are mismatched.

Case-3:

  always@(a,b,c,d,x,y) begin //or always@(*) begin

    x <= a & b;

    y <= c & d;

    f <= x & y;

  end

Simulation results:

First always block executed then x and y are evaluated as 1 and 0, f as 1 which is past output. Here y value is changed so always block get executed one more time then f become 0. Here always block gets executed twice, so simulation time become double i.e., performance degrades.

Synthesis results:

Synthesis results for the above all three cases are same as shown below.