Modeling a Flop:

Assume that the flop which is going to be modeled is shown in below figure.

Case-1: modeling using assign statement

assign q = ( !rst ) ?  ( clk ? d : q ) : 0;

Here simulation results are matched but synthesis results are mismatched because assign statement is used to model combo logic so in synthesized output we get muxes. This is not correct modeling of flop.

Case-2: modeling using always with BA

always@(posedge clk) begin

  if(rst) q = 0;

  else q = d;

end

Here one always block was there so we get correct simulation and synthesis results. If multiple always block were there and q is assigned to another variable in other always block then we get wrong simulation results because of race condition. This is also not correct modeling of flop.

Case-3: modeling using always with NBA

always@(posedge clk) begin

  if(rst) q <= 0;

  else q <= d;

end

Here both synthesis and simulation results are matched even if there are multiple always blocks. This is the correct way of modeling a flop.