Delays in verilog:

Delays in verilog are not synthesize able, so we use them mainly for verification. In design we generate delays using counters because no gate/flop will not generate 1 sec delay. Assume a gate produce 1 ps delay then in order to generate 1ns delay synthesizer will connect 1000 gates which makes design complex. So, by taking output of counter we generate delays in hardware.

Delays are represented as #1, #2, #3,.....where #1 indicates 1 time unit delay. The value of 1 time unit is mainly depends on `timescale construct. By using `timescale construct we can change the simulator frequency as follows:

Syntax: `timescale <value>/<precision>

Example: `timescale 1ns/1ns

• Here value should be in multiples of 10 only
• units of value are ms, ns, ps,.....
• precision should not be greater than value
• blindly multiply the value with delay that will give us value of one time unit
• precision will tell you granularity levels of each clk

Example:

 `timescale 10ns/1ns

 reg y;

 y = 1;

 #10 y = 0;

 #1.26 y = 1;// Rounded to nearest integer i.e., 13

`timescale 1ns/1ns

 reg x;

 x = 0;

 #10 y = 1;

 #1.2 y = 0;//Rounded to nearest integer i.e., 1

There are 2 types of delays they are

• inter assignment delay
• intra assignment delay

Inter assignment delay:

Example: 

x = 1;

#10 x = 0; 

Here in current time unit 1st statement is executed and 2nd statement is postponed to 10 time units.

Intra assignment delay:

Example:

x = #10 1;

Here in current time tick x value is evaluated as 1 and it is assigned after 10 time units.

 We can also use delays in continuous assignments in order to avoid glitches.

Example:

assign #10 x = y + z;

Normal assign statement executed when ever there is change in y and z. If we introduce delay in assign statement then even if there is change in y and z before 10 time units it never considers. It considers values of y and z for every 10 time units but it never considers values in between 10 time units.